Analyze and Implementation of FPGA Implementation of HUB Floating-Point Addition
T. Srinivas Reddy1, CH. Shekar2, J. Prabhakar3
1Dr. T. Srinivas Reddy, Associate Professor, Department of ECE, Malla Reddy Engineering College (A), Main Campus, Hyderabad (Telangana), India.
2CH. Shekar, Assistant Professor, Department of ECE, Teegala Krishna Reddy Engineering College, Hyderabad (Telangana), India.
3J. Prabhakar, Assistant Professor, Department of ECE, Nalla Malla Reddy Engineering College, Hyderabad (Telangana), India.
Manuscript received on 02 March 2019 | Revised Manuscript received on 14 March 2019 | Manuscript Published on 17 March 2019 | PP: 206-209 | Volume-7 Issue-ICETESM18, March 2019 | Retrieval Number: ICETESM45|19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: FPGA is progressively existence used to design high performance and computationally intense processors proficient of management in cooperation fixed and floating point mathematical operations. The prominent necessity of Half-Unit-Biased due to its flexibility with the shifting operations of numbers in half unit. This paper analysis the profits of by means of pipeline format to implement floating point (FP) arithmetic below a round to nearest mode from a measureable point of interpretation. With the pipelining format to represent numbers permits the removal of rounding logic of arithmetic units, including sticky bit computation.
Keywords: HUB Format, Floating Point (FP), FPGA, Pipelining.
Scope of the Article: FPGAs