Timing Closure of Memory Partitions for a Lower Nodes Technologies
Piyush Bhatasana,Department of Electronics and Communication Engineering, Nirma University, Ahmedabad, Gujarat, India.
Manuscript received on February 28, 2020. | Revised Manuscript received on March 22, 2020. | Manuscript published on March 30, 2020. | PP: 5322-5325 | Volume-8 Issue-6, March 2020. | Retrieval Number: F9913038620/2020©BEIESP | DOI: 10.35940/ijrte.F9913.038620
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Metal interconnects are used to make the interconnections between different part of the circuitry to realize any System on Chip (SoC) design. For the advanced process technologies, the metal interconnects affects the performance of the design. For nanometer process technologies, the coupling effect in the interconnect causes crosstalk and noise. These noise and crosstalk must be affect the operating speed of the design. This is most responsible candidate for the timing aspect of the design. Thus, the physical design and verification of the advanced process technologies should be include the effects of noise and crosstalk. If the timing of a design is not verified, then the design may not perform at the desired operating speed. The power and area are the other factors, that also to be consider with timing for a faster design. There will always be a trade-off between these three factors. Static Timing Analysis (STA) is one of the many techniques used by the designers to verify the timing of the design and also for closing the design with respect to timing, which is called as timing closure.
Keywords: Static Timing Analysis (STA), Noise and crosstalk, Setup and Hold check, Signoff, Engineering Change Order (ECO), DTA.
Scope of the Article: Software Engineering Methodologies.