Parallelism Effects in Higher Term Dot Product Floating Point Computation
Prasanna Palsodkar1, Prachi Palsodkar2
1Prachi Palsodkar*, Department of Electronics Engg, Yeshwantrao Chavan College of Engineering, Nagpur, India.
2Prasanna Palsodkar, Department of Electronics Engg, Yeshwantrao Chavan College of Engineering, Nagpur, India.
Manuscript received on April 02, 2020. | Revised Manuscript received on April 15, 2020. | Manuscript published on May 30, 2020. | PP: 94-100 | Volume-9 Issue-1, May 2020. | Retrieval Number: F9496038620/2020©BEIESP | DOI: 10.35940/ijrte.E9496.059120
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In complex signal processing applications, Floating Point (FP) arithmetic is a complex, but extremely accurate representation, which needs to be optimizing by architectural modification. This paper describes discrete to fused arithmetic implementation with two, three and four operand FP methodology. Parameters like Area, Power and Delay (APD) are considered for analysis. Exhaustive analysis is carried out here from basic FP component to complete structuring of Four Term Dot Product FP (FTDPFP). Analysis shows that FTDPFP computation improves speed by 89-91% compared to three term and two term computation. Area wise overheads increases in FTDPFP and it is optimized by using new exponent, dual reduction, early normalization, Leading zero participator (LZA), rounding and compounding techniques. Power consumption is optimized with same competency of Two and Three Term Dot Product Floating Point (TTDPFP).
Keywords: Floating Point, Two Term, Dot Product, Three Operand, Four Term.
Scope of the Article: Computational Geometry.