Design Optimization Of Triple Material Gate Stacked Oxide TFET
A Maria Jossy1, Swati Sajee Kumar2, Ananya Chakraborty3, Namrata Lahiri4

1Namrata Lahiri, Department of ECE, SRM Institute of Science and Technology, Chennai, (Tamil Nadu), India.
2A Maria Jossy1 , Department of ECE, SRM Institute of Science and Technology, Chennai, (Tamil Nadu), India.
3Swati Sajee Kumar, Department of ECE, SRM Institute of Science and Technology, Chennai, (Tamil Nadu), India.
4Ananya Chakraborty, Department of ECE, SRM Institute of Science and Technology, Chennai, (Tamil Nadu), India.

Manuscript received on 23 March 2019 | Revised Manuscript received on 30 March 2019 | Manuscript published on 30 March 2019 | PP: 1947-1950 | Volume-7 Issue-6, March 2019 | Retrieval Number: F2719037619/19©BEIESP
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Abstract: In this paper, we propose the design and purpose for devising a Triple Material Gate Stacked Oxide (TMGSO) Tunnel Field Effect Transistor (TFET) to simultaneously optimize the On current (ION), Off current (IOFF) and the threshold voltage. Moreover, the design also improves the subthreshold slope, the ION-IOFF ratio and also provides immunity from the Short Channel Effects (SCEs). We also compare the transfer characteristics of our structure with the previously developed structures and justify the reasons behind the variations. Furthermore, the relationship between the work function of the metal and the electric field has also been studied by comparing the simulation results of Single Metal Gate (SMG) TFET with the TMGSO TFET. The design and simulation of TFET is done on Technology Computer Aided Design (TCAD Sentaurus) Simulator
Keywords: On current, Off current, Threshold voltage, Sub-threshold slope, Short Channel Effects, Work function.
Scope of the Article: Mechanical Design