FPGA-Based Implementation of Intra Prediction Module for HEVC Decoder
Manel Kammoun1, Ahmed Ben Atitallah2 

1Manel Kammoun, LETI Laboratory, University of Sfax, Sfax, Tunisia
2Ahmed Ben Atitallah, College of Engineering, Jouf University, Kingdom of Saudi Arabia.

Manuscript received on 17 March 2019 | Revised Manuscript received on 20 March 2019 | Manuscript published on 30 July 2019 | PP: 6130-6137 | Volume-8 Issue-2, July 2019 | Retrieval Number: F2440037619/19©BEIESP | DOI: 10.35940/ijrte.F2440.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The High Efficiency Video Coding (HEVC) is the new standard which is designed to support High Definition (HD) and Ultra-HD video cotenants. In HEVC, several new coding tools are adopted in order to improve the coding efficiency and compression ratio but with a significant increase in the computational complexity comparing to the previous standard H.264/AVC. In this paper, we focus on reducing the complexity of the most consuming block in the HEVC decoder standard which is the intra prediction module. In this context, we propose an optimized hardware architecture dedicated to support the 34 modes of intra prediction module considering 4×4, 8×8 and 16×16 block sizes. The proposed design exploits the symmetric property between horizontal and vertical modes. Hence, we implement a new hardware architecture that factorizes the same hardware resources for both directions which leads to save the hardware cost, the power consumption and the processing time. Furthermore, the different block sizes are implemented independently in order to avoid memory overhead while accessing to the shared memory. The implemented design using Xilinx Zynq-based FPGA platform can process in real time the Ultra-HD video frame of resolution (4096×2048) at 232 MHz. As well, the synthesis results using the TSMC 180 nm CMOS technology provide similar performance than our FPGA implementation. Finally, the HW/SW implementation of full HEVC decoder can process the decoding of 15 FPS in best case for 240p video resolution with a gain of 60% in power consumption.
Keywords: HEVC; Intra Prediction; Zynq FPGA.

Scope of the Article:
Regression and Prediction