High Speed Event Driven Data Acquisition system based on ZYNQ SOC Architecture
Himanshu Tyagi1, Nagendra Gajjar2, Suryakant Gupta3

1Himanshu Tyagi, Department of ECE, Nirma Unversity, Ahmedabad, (Gujrat), India.
2Nagendra Gajjar, Department of ECE, Nirma Unversity, Ahmedabad, (Gujrat), India.
3Suryakant Gupta, Institute For Plasma Research Gandhinagar, (Gujrat), India.

Manuscript received on 23 March 2019 | Revised Manuscript received on 30 March 2019 | Manuscript published on 30 March 2019 | PP: 2018-2022 | Volume-7 Issue-6, March 2019 | Retrieval Number: F2556037619/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Acquisition and streaming of signals at high sampling rates at ~100MS/s is a challenging task due to memory and network bottlenecks. At such high rates it is important that data acquisition systems be activated only for a limited duration during an external event which is dictated by the amount of on board memory available for logging of data samples. The platforms for such applications need high speed ADC modules, sufficient on board RAM to log samples and a controller. Although commercial platforms do exist for meeting such requirements most of them are quite expensive. Contemporary system on chip (SOC) based solutions such as Xilinx ZYNQ provides an option of tightly coupled FPGA and ARM processor. The advantage of such architecture is that the FPGA can be available for handling critical time bound tasks and the processor can handle configuration management.The present work focuses on development of event driven high speed acquisition system based on Zynq SOC with user configurable options. For development of the prototype, Red Pitaya board is selected which hosts 2 on board ADC modules with 512MB RAM. The data is acquired at 125 MS/s rate for user defined event durations. Other parameters such as pre and post trigger duration, buffer length are also user configurable. The performance of such systems is also based on the type of file system utilized for storing the data. Hence in the present work details of various file formats used and their effect has been studies. Open source libraries based on Python are used to develop windows based TCP client program with Qt GUI framework for transmission of configuration parameters to Zynq platform and exchange the status of program. The server program is being executed using a C program which communicates to the ARM processor. In this paper the details of the system design, architecture, software flow and analysis of results are mentioned.
Keywords: FPGA, ZYNQ, SOC, Data Acquisition, High Speed
Scope of the Article: High Speed Networks