Sloating Point Multiplier Implementation A Broader Perspective
S. Umadevi1, T. Vigneswaran2
1S. Umadevi, Assistant Professor in the Department of ECE, SRM University, Chennai, India.
2T. Vigneswaran, Professor, School of Electronics Engineering, VIT University, Chennai. India.
Manuscript received on 03 April 2019 | Revised Manuscript received on 11 May 2019 | Manuscript published on 30 May 2019 | PP: 3330-3341 | Volume-8 Issue-1, May 2019 | Retrieval Number: F2150037619/19©BEIESP
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Abstract: Floating point multiplication is a crucial and more frequently used arithmetic operations in high power computing applications such as signal processing, image processing etc. High speed and memory requirement of IEEE-754 standard floating point multiplier makes its implementation more complex in many systems which require fast computing. Hence bringing an efficient architecture to complete the floating point multiplication operation with less computation time and with less memory requirement turned into one of the main research area in almost all the field of electronics. In this research review paper detail explanation about each and every architecture proposed for floating point multiplier is presented and its pros and corns are discussed. Later, comparison study between five different parallel floating point multiplier architectures which has been implemented on tsmc 180nm technology node is presented. From the results it has been observed that among all five proposed floating point parallel multiplication, a New Computation Sharing High speed Multiplier (CSHM) architecture based floating point implementation can yield a better results interms of all the performance parameters is concerned and better suitable for Finite Impulse Response (FIR) filtering operation. Cadence®nclaunch, rc compiler and Encounter are the tools used for simulating, synthesizing and physical design implementation.
Key words: Floating Point, Parallel Architecture, FIR Filter
Scope of the Article: Software Engineering Techniques and Production Perspectives