Design and Simulink Implementation of 128-bit Vedic Multiplier
Gouri G Uppin1, Mahesh N. Javalkar2

1Gouri G. Uppin, Lecturer, Department of Electronics and Communication Engineering, Maratha Mandal Polytechnic, Belgaum, (Karnataka) India.
2Mahesh N. Javalkar, Lecturer, Department of Electronics and Communication Engineering, Maratha Mandal Polytechnic, Belgaum, (Karnataka) India.

Manuscript received on 20 January 2016 | Revised Manuscript received on 30 January 2016 | Manuscript published on 30 January 2016 | PP: 15-18 | Volume-4 Issue-6, January 2016 | Retrieval Number: F1516014616©BEIESP
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Abstract: In the calculation of real numbers, carry needs to be propagated from the least significant bit (LSB) to the most significant bit (MSB) when binary partial products are added. Thus because of this process, the addition and subtraction after binary multiplications limit the overall speed. Existing vedic multiplication is available for 8bits, 16bits, 32bit and 64 bits, proposed system is for 128bits multiplication and to increased time efficiency, with less consumption of power. Nikhilam Sutra literally means “all from 9 and last from 10”. Although it is applicable to all cases of multiplication, it is more efficient when the numbers involved are large. Since it finds out the compliment of the large number from its nearest base to perform the multiplication operation on it, larger is the original number, lesser the complexity of the multiplication. Thus, by using Nikhilam sutra it possible to multiply large numbers which is the limitation in the simple array multipliers. Nikhilam Navatashcaramam Dashatah- All from 9 and the last from 10 From the sixteen sutras available in Vedic mathematics, among them only two sutras are applicable for multiplication operation. They are Urdhva Triyakbhyam Sutra (literally means vertically and cross wise) and Nikhilam Sutra (literally means all from 9 and last from 10).Vedic Mathematics provides some effective algorithms which can be applied to various application fields of engineering. Out of these algorithms former proves to be a faster algorithm and applicable in all cases.
Keywords: Vedic Multiplie (V M ), Radix selection unit (RSU), Exponent Determinant (E D), Mean Determinant (MD) Multiplexer ( MUX )

Scope of the Article: Low-power design