Design and Implementation of Optimized Area and PDP Multiplier for High Speed Digital Circuit Applications
M. Kathirvelu

M. Kathirvelu, Department of Electronics and Communication Engineering, GMR Institute of Technology, Rajam (Andhra Pradesh), India.
Manuscript received on 08 May 2019 | Revised Manuscript received on 19 May 2019 | Manuscript Published on 23 May 2019 | PP: 1081-1085 | Volume-7 Issue-6S5 April 2019 | Retrieval Number: F11850476S519/2019©BEIESP
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Abstract: Low power, High speed Multipliers are needed for high speed switching applications like Digital Signal Processing (DSP), microprocessors and filters. Various multiplier architectures are implemented by various research people. In the 8-bit array multiplier, partial products are obtained through AND gates and it is added sequentially through Full Adders and Half Adders. The array multiplier depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the proposed architecture, partial products are added parallel to obtain the product with lesser delay. The power dissipation of full adder is minimized by implementing with the CMOS technology. The designed 8-bit multiplier is implemented and simulated with the Cadence Virtuoso tool in 90nm technology and its performance like Power, speed and area are analyzed.
Keywords: Full Adder, Half Adder, Multiplier, Carry Lookahead Adder.
Scope of the Article: Microstrip Antenna Design and Application