Design and Simulation of Energy-Efficient 8-Bit Input Buffer for NoC Router
Sanghapal D. Kamble1, M.A.Gaikwad2
1Sanghapal D. Kamble, Student M. Tech., B.D. College of Engineering Wardha (Maharashtra), India.
2M.A. Gaikwad, Principal B.D. College of Engineering Wardha (Maharashtra), India.
Manuscript received on 20 January 2014 | Revised Manuscript received on 25 January 2014 | Manuscript published on 30 January 2014 | PP: 126-129 | Volume-2 Issue-6, January 2014 | Retrieval Number: F0944012614/2014©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In NoC (Network on chip), the power consumption is major issue while designing. In NoC router, conventional input buffer consume more energy. The paper is focused on the energy-efficient design of 8-bit input buffers, which use the characteristic of transmission of data on NoC that has probability of transmitting a zero signal is more than that of transmitting a signal one. The design of energy efficient 8-bit input buffer reduces the power consumption by 48% and the chip area 29% with calculating the gates count as compared with conventional 8-bit input buffer by using 65 nm cmos technology in simulation.
Keywords: Network on Chip, NoC Router, Input Buffer.
Scope of the Article: Network Modelling and Simulation