Efficient Programmable Finite Impulse Response Filter using Xilinx MAC FIR Filter for Software Defined Radio
Baha Ali Nasir

Baha Ali Nasir, Department of Electronic Technique, Institute of Technology, Baghdad, Iraq.
Manuscript received on 20 January 2014 | Revised Manuscript received on 25 January 2014 | Manuscript published on 30 January 2014 | PP: 22-26 | Volume-2 Issue-6, January 2014 | Retrieval Number: F0905012614/2014©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This paper presents a development of FIR filter using polyphase multiply accumulate (MAC) block in system generator to decrease the multiplication process and hence power consumption to provide the SDR requirements. The entrenched system generator offers a very attractive solution that balance high flexibility and performance of FIR filter to minimize the multiplication process. This paper focuses on efficient design of digital FIR filter for software defined radio on an FPGA target device. The simulation results shows an important development in minimization of FIR filter multiplication to utilize the look up table (LUPs) and Slices in FPGA area which decrease the power consumption compared with conventional design.
Keywords: PFIR, MAC, SDR.

Scope of the Article: Software Engineering & Its Applications