A Novel IEEE-754 Floating-Point Butterfly Architecture based on Multi Operand Adders
Thota Swetha1, S. Srinivas2

1Thota Swetha, PG Scholar, SR Engineering College, Ananthasagar, Hasanparty, Warangal (Telangana), India
2S. Srinivas, Associate Professor, SR Engineering College, Ananthasagar, Hasanparty, Warangal (Telangana), India
Manuscript received on 05 February 2019 | Revised Manuscript received on 18 February 2019 | Manuscript Published on 04 March 2019 | PP: 55-60 | Volume-7 Issue-5S2 January 2019 | Retrieval Number: ES2007017519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: FFT (Fast Fourier Transform) is one of most efficient algorithm widely used in communication systems. FFT function consists of Butterfly units with multiply add operations over complex numbers. A floating point is applied to FFT design, mainly to butterfly units. The concentrated tasks are calculated from general purpose processor by order FP concerns. The significant drawback of FP butterfly is its slowness in its examination with its fixed point. In proposed FP butterfly uses a fused dot product add(FDPA) unit to calculate butterfly unit, depending on binary signed digit(BSD).A BSD adder is introduced and utilized as a part of the three operand adder and parallel BSD multiplier, in order to enhance the speed of the FDPA unit. A modified booth encoding is utilized to accelerate BSD multiplier. The results shows that proposed FP butterfly design is considerably speedier than past butterfly design.
Keywords: Binary-Signed Digit (BSD) Representation, Butterfly Unit, Complex Number System, Fast Fourier Transform (FFT), Floating-Point (FP), Redundant Number System, Three-Operand Addition.
Scope of the Article: Open Models and Architectures