DSP TMS320C6678 Based SHVC Encoder Implementation and its Optimization
Ibtissem Wali1, Amina Kessentini2, Mohamed Ali Ben Ayed3, Nouri Masmoudi4

1Ibtissem Wali*, University of Sfax, National Engineering School of Sfax Electronics and Information Technology Laboratory, LETI Sfax, Tunisia.
2Amina Kessentini, University of Sfax, National Engineering School of Sfax Electronics and Information Technology Laboratory, LETI Sfax, Tunisia.
3Mohamed Ali Ben Ayed, University of Sfax, National Engineering School of Sfax Electronics and Information Technology Laboratory, LETI Sfax, Tunisia.
4Nouri Masmoudi, University of Sfax, National Engineering School of Sfax Electronics and Information Technology Laboratory, LETI Sfax, Tunisia.
Manuscript received on March 02, 2020. | Revised Manuscript received on November 24, 2021. | Manuscript published on January 30, 2022. | PP: 24-31 | Volume-10 Issue-5, January 2022. | Retrieval Number: 100.1/ijrte.E66560110522 | DOI: 10.35940/ijrte.E6656.0110522
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The programmable processors newest technologies, as for example the multicore Digital Signal Processors (DSP), offer a promising solution for overcoming the complexity of the real time video encoding application. In this paper, the SHVC video encoder was effectively implemented just on a single core among the eight cores of TMS320C6678 DSP for a Common Intermediate Format (CIF)input video sequence resolution(352×288). Performance optimization of the SHVC encoder had reached up 41% compared to its reference software enabling a real-time implementation of the SHVC encoder for CIF input videos sequence resolution. The proposed SHVC implementation was carried out on different quantization parameters (QP). Several experimental tests had proved our performance achievement for real-time encoding on TMS320C6678.
Keywords: Scalable Video Coding, SHVC encoder, DSP-TMS320C6678 algorithm optimization.