Design and Simulation of Pipelined Floating-Point Multiplier using Logisim
Shivani Desai1, Qasim Bhatia2
1Shivani Desai*, CSE Department, Nirma University, Ahmedabad, India.
2Qasim Bhatia, CSE Department, Nirma University, Ahmedabad, India.
Manuscript received on January 02, 2020. | Revised Manuscript received on January 15, 2020. | Manuscript published on January 30, 2020. | PP: 1087-1090 | Volume-8 Issue-5, January 2020. | Retrieval Number: E5942018520/2020©BEIESP | DOI: 10.35940/ijrte.E5942.018520
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Floating point multiplication is a cycle intensive operation used in signal and image processing. The operation time of multiplication could be increased by pipelining this process. In this paper, we design and simulate a pipelined floating-point multiplier using the Logisim simulation tool. The numbers are stored in the IEEE 754 single-precision format. This circuit can be implemented into newer microprocessors to be used as a fast multiplier. An array of these multipliers can be used in matrix multiplications in artificial neural networks and other applications where rapid multiplication is required. The Logisim simulation tool is used as it is easy to use and has a simple interface with powerful abstraction features. It is used in major universities to teach and simulate computer architecture.
Keywords: Floating-Point Multiplier, Pipeline Clock Cycle.
Scope of the Article: Digital Clone or Simulation.