Survey on Particle Swarm Optimization Techniques in Network-on-Chip
K. Sathis Kumar1, K. Paramasivam2

1K Sathis Kumar, Department of Computer Science and Engineering, Bannari Amman Institute of Technology, Sathyamangalam (Tamil Nadu), India.
2Dr. K. Paramasivam, Department of Electrical and Electronics Engineering, Kumaraguru College of Technology, Coimbatore (Tamil Nadu), India.
Manuscript received on 10 December 2018 | Revised Manuscript received on 29 December 2018 | Manuscript Published on 09 January 2019 | PP: 56-58 | Volume-7 Issue-4S November 2018 | Retrieval Number: E1869017519/19©BEIESP
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Abstract: Network-on-Chip (NoC) an interconnection framework is proposed by Numerous number of Intellectual Property cores in the nature of System-on-Chip(SoC). Communication challenges in a global nature with respect to nanoscale technology is provided by NoC. A configuration of NoC with its least average traffic in communication, consumption of power and area covered in chip is the needed in real time applications. Effective routing, mapping the cache hierarchy, memory and application mapping are the main parameter to increase the efficiency in aNoC. This can be done with optimization techniques. With optimization technique, NoC can be configured such that the latency, consumption of power, and chip area engaged in aNoC are made to be minimal. This paper provides a survey of Particle Swarm Optimization (PSO) algorithm techniques to optimize NoC routing, Mapping of memory and application mapping to provide performance improvement.
Keywords: Network-on-chip (NoC); Cache Hierarchy; Algorithms in Routing; Particle Swarm Optimization (PSO); Quality of Service (QoS), NoC Design, Chip Multiprocessor.
Scope of the Article: Swarm Intelligence