On Timing Closure: Hold-Violation Removal using Insertion of Buffers, Inverters and Delay Cells
S. Aruna Mastani1, Patra Suresh Reddy2

1Dr. S.Aruna Mastani, Assistant Professor, Department of ECE, JNTUA College Of Engineering, Ananthapuramu (A.P), India.
1Patra Suresh Reddy, Student, M.tech in Digital Electronics and Communication Engineering, JNTUA College of Engineering, Ananthapuramu (A.P), India.

Manuscript received on 24 September 2018 | Revised Manuscript received on 30 September 2018 | Manuscript published on 30 November 2018 | PP: 195-199 | Volume-7 Issue-4, November 2018 | Retrieval Number: E1827017519©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Timing closure plays a major role in the Physical design synthesis. In the process of timing optimization, buffers, inverters, delay cells are used as delay elements inorder to speedup the circuit. Given with the violated path proper selection of combination of delay elements is to be made to meet the hold requirement of the path. Here, in this work a standard industrial design is taken having 5241 violated paths. For these paths, hold time is computed as per the linear programming optimization. Timing closure is done by various combinations of buffers, inverters and delay cells. Discrete buffers, Complex timing constraints and accurate timing models/analysis make time consuming and problem difficult to solve. The linear programming-based methodology is presented to model the setup and hold-time constraints. Then based on the solution to the linear programming optimization, buffers, inverters and delay cells are inserted as delay elements to solve hold violations. The implemented approach where delay cells, buffers, inverters are used as delay elements for optimization and using only buffers as delay elements in optimization process are tested on industrial design together with the industrial hold optimization flow, and better results achieved in terms of minimum hold slack, hold violations and utilization are reported.¬¬ Compared to the delay insertion using buffers only, the implemented approach can obtain 31% worst hold slack reductions and better utilization for the industrial circuit level design. Analysis of timing paths and removal of hold violation problem in physical design flow is implemented using TCL and PERL scripts in cadence encounter tool.
Keywords: Delay Insertion, Hold Violation, Physical Design, Utilization.

Scope of the Article: Cyber Physical Systems (CPS)