Design and Analysis of Low Power Full Adder for Portable and Wearable Applications
A. Benjamin Franklin1, T. Sasilatha2

1A. Benjamin Franklin, Research Scholar, Department of EEE, AMET Deemed to be University, Chennai (Tamil Nadu), India.
2Dr. T. Sasilatha, Professor and Dean, Department of EEE, AMET Deemed to be University, Chennai (Tamil Nadu), India.
Manuscript received on 23 April 2019 | Revised Manuscript received on 02 May 2019 | Manuscript Published on 08 May 2019 | PP: 295-299 | Volume-7 Issue-5S3 February 2019 | Retrieval Number: E11540275S19/19©BEIESP
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Abstract: In this paper, our objective is to design a low power full adder with minimum number of transistors and to analysis the calculated values such as Power, Delay and Power Delay-product (PDP) using 45 nm CMOS process technology. The adder cell is compared with several types widely used adders with different configuration of transistors. The proposed full adder cell has low power consumption, better area efficiency. Designed full adders were evaluated through post-layout Spectre simulations with a 45 nm CMOS technology using Cadence tool. This result shows 20% to 30% improvement in power consumption designed adder that makes it to be used for wide range of applications.
Keywords: Full Adder, Power Delay Product (PDP) and area, CMOS LOGIC, Low Power, Transistor Configuration.
Scope of the Article: Low-power design