A Low Power and High Speed Array Multiplier Using on-the-Fly Conversion
S Aruna1, S Venkatesh2, K. Srinivasa Naik3

1Dr. S Aruna, Department of ECE, Andhra University College of Engineering (A), Visakhapatnam (Andhra Pradesh), India.
2Mr. S Venkatesh, Department of ECE, Andhra University College of Engineering (A), Visakhapatnam (Andhra Pradesh), India.
3Dr. K. Srinivasa Naik, Department of ECE, Vignan”s Institute of Information Technology (A), Visakhapatnam (Andhra Pradesh), India.
Manuscript received on 14 February 2019 | Revised Manuscript received on 05 March 2019 | Manuscript Published on 08 June 2019 | PP: 345-349 | Volume-7 Issue-5S4, February 2019 | Retrieval Number: E10720275S419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: A low power and high speed On-The-Fly Conversion (OTFC) array multiplier is proposed with optimum design resulting in reduced delay, low power intake and dwindled silicon area. In the multiplier design (single precision truncated) recommended earlier, the product of 2N-bits produces 2N but partial products, excluding this 2N bit partial products, are going to be divided into 2N-(N/2) bits and N/2 bits. As a result finally, 2N bits are created by the adding of above bits using ripple carry adder. The array multiplier outlined in this paper is designed and implemented with no truncation or addition technique, instead, it is executed using a typical array multiplier scheme. The proposed array multiplier in this paper produces the high order bit (MSB) of the final product. The multiplier design outlined in this paper leverages the On the Fly Conversion converter that is implemented at the tail end of the multiplier. This is to achieve the expedited carry propagation in the last leg of the multiplication. To highlight and contrast the benefits of the proposed array multiplier we have considered the previous designs proposed for different bits (8, 16 and 32) for features and critical parameters like silicon area, delay and power. As part of the implementation, we are able to attain remarkable results with low power consumption, minimum delay, smaller area and less energy.
Keywords: Array Multiplier, Truncation, OTF Conversion, Ripple Carry Adder.
Scope of the Article: Low-power design