Advanced Encryption Standard for Data Encryption using EDK Environment in FPGA
1B.Satyanarayana, Department of ECE, Sri Satya Sai University of Technology and Medical Science, Sehore, Bhopal, Madhya Pradesh, India.
2Dr M.Srinivasan , Department of ECE, Sri Satya Sai University of Technology and Medical Science, Sehore, Bhopal, Madhya Pradesh, India.
Manuscript received on November 17., 2019. | Revised Manuscript received on November 24 2019. | Manuscript published on 30 November, 2019. | PP: 11969-11972 | Volume-8 Issue-4, November 2019. | Retrieval Number: D9920118419/2019©BEIESP | DOI: 10.35940/ijrte.D9920.118419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Now a day’s VLSI is developing technology as predicted by Moors law which is drastically increasing as per demand one of that is data security for efficient processing so, data encryption and decryption are major play in security for this an advanced encryption standard is there which uses reconfigurable hardware process in this paper field programmable gate arrays (FPGAs) kit of Xilinx based platform in which spartan3E EDK kit is used. Here we analyze the speed of AES algorithm by using this EDK environment where obvious high speed is considerable and with power consumption and throughput exemptions. With micro blaze soft core processer we implement our algorithm of AES by using c coding we configure the hardware structure. EDK tool with one round operation is done and both area utilization and throughput are observed as we are familiar that when area reduces power consumption also reduces.
Keywords: Advanced Encryption Standard, VHDL, FPGA, power gain, throughput.
Scope of the Article: FPGAs.