Design and Implementation of Hybrid FIR Filters using Vedic Multiplier and Fast Adders
S. Jayakumar1, R. Selvam2, K. Karthikeyan3, R. Natesan4
1S. Jayakumar, Assistant Professor (S.G), Department of E. I. E, KCG College of Technology, Karapakkam, Chennai, Tamil Nadu, India.
2R. Selvam, Assistant Professor, Department of E. E. E, Karapakkam, KCG College of Technology, Chennai, Tamil Nadu, India.
3K. Karthikeyan, Associate Professor, Department of E. I. E, KCG College of Technology, Karapakkam, Chennai, Tamil Nadu, India.
4R. Natesan, Assistant Professor, Department of E. E. E, KCG College of Technology, Karapakkam, Chennai, Tamil Nadu, India.

Manuscript received on November 17., 2019. | Revised Manuscript received on November 24 2019. | Manuscript published on 30 November, 2019. | PP: 11849-11853 | Volume-8 Issue-4, November 2019. | Retrieval Number: D9569118419/2019©BEIESP | DOI: 10.35940/ijrte.D9569.118419

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Abstract: FIR (Finite Impulse Response) filters play a significant role in the field of Digital Signal Processing (DSP) to eliminate noise suppression in Electro Cardio Graph (ECG), Imaging devices and the signal stored in analog media. So filter evaluation is accomplished to reduce the noise level. The Filter passes only the desired frequency to pass thereby reducing distortion in the processed signal during measurement. The FIR filter comprises of basic units like adders, multipliers and the delay element for its operations.FIR and IIR are the two types of digital filters chosen based on the range of inputs, complexity and size requirement. Multipliers and adders play a vital role in deterring the performance of FIR filter. In this work, we design and analyze different multiplier and adder for high-performance Fir filter implementation. The Vedic Mathematics is the methods containing 16 Sutras to aid fast mental calculations. In this work, we propose modified Anurupye Vedic multiplier methods with Kogge Stone fast adder for implementation in the direct form FIR filter. This approach provides 1.5% decrease in delay and 10.2% reduced in power, hence increasing speed marginally than previous methods. Along with low power consumption in Very High-Speed Hardware Description Language (VHDL), all the adders and the multiplier topologies are Synthesized using (Xilinx Spartan – 6 FPGA) Trainer Kit and the proposed 8 – Tap FIR filter is executed using this Board.
Keywords: FIR, Anurupue Vedic Multiplier, Kogge Stone adder, VHDL, Xilinx Spartan –6 FPGA.
Scope of the Article: FPGAs.