Design of Advanced 64-bit Full Adder in 45-nm Technology
Paruchuri Uma Devi1, Joseph Anthony Prathap2
1Paruchuri Uma Devi, Digital electronics and communication, Vardhaman College of Engineering, Hyderabad, India.
2Dr. Joseph Anthony Prathap, Associate Professor, Electronics and Communication Engineering, Vardhaman College of Engineering, Hyderabad, India.

Manuscript received on November 17., 2019. | Revised Manuscript received on November 24 2019. | Manuscript published on 30 November, 2019. | PP: 12173-12178 | Volume-8 Issue-4, November 2019. | Retrieval Number: D8709118419/2019©BEIESP | DOI: 10.35940/ijrte.D8709.118419

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Abstract: This paper presents the design of a 64-bit parallel adder with 45_nm technology using cadence virtuoso tool. The proposed method uses the designed 1-bti full adder and the performance is compared with the other cadence virtuoso technologies i.e. 180-nm and 90-nm. Performance parameters such as average power, delay, PDP and transistor count are calculated and compared with the 180-nm and 90-nm technologies. The proposed method based on 45-nm technology at 1V supply exhibits the average power consumption as low as 0.114μW and less delay of 3.503ps which is obtained from the absorption of extremely feeble CMOS inverters together with physically powerful transmission gates. The full adder is designed by using XNOR module and transmission gates. The XNOR module is used to produce the output SUM and the transmission gates are used to produce the output Carryout.
Keywords: Full Adder, XNOR Module, Transmission gate, 45 nm Technology.
Scope of the Article: Wireless Power Transmission.