A Low Jitter – Low Phase Noise Wideband Digital Phase Locked Loop in Nanometer Cmos Technology
Nilesh D. Patel1, Amisha P. Nai Priyesh P. Gandhi2
1Dr. Nilesh D. Patel, Principal M. L. Institute of Diploma Studies Bhandu, India.
2Dr. Amisha P. Naik, Associate Professor, Institute of Technology, Nirma University Ahmedabad, India.
3Dr. Priyesh P. Gandhi, Principal Sigma Institute of Engineering Vadodara, India.
Manuscript received on November 10, 2019. | Revised Manuscript received on November 17, 2019. | Manuscript published on 30 November, 2019. | PP: 3994-3999 | Volume-8 Issue-4, November 2019. | Retrieval Number: D8615118419/2019©BEIESP | DOI: 10.35940/ijrte.D8615.118419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: For high speed communication applications; jitter, phase noise and power consumption are most critical parameters required to be considered for PLL designs. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. This article presents similar design for 7.5-GHz Phase locked loop in 180 nm CMOS technology. The measured phase noise of the proposed PLL with self aligned injection at 1 MHz offset is 121.14 dBc/Hz and rms jitter is 110 fs. The total dc power consumption is 13.99 mW. To support the claim process variation with design corner analysis using random variations are carried out.
Keywords: Component; CMOS, PLL, Loop Filter, Voltage Control Oscillator, Phase Frequency Detector, Low Pass Filter, Delay Locked Loop.
Scope of the Article: Frequency Selective Surface.