Performance of Improved speed pipelined floating point multiplier Architecture
Dr. Rajendra Prasad. K, Assistant Professor, Department of Electronics and Communications Engineering, Malla Reddy Engineering College (A),Telangana India.
Manuscript received on November 12, 2019. | Revised Manuscript received on November 25, 2019. | Manuscript published on 30 November, 2019. | PP: 6018-6021 | Volume-8 Issue-4, November 2019. | Retrieval Number: D8055118419/2019©BEIESP | DOI: 10.35940/ijrte.D8055.118419
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Multiplier is a hardware component which usually covers an important chip area and must be reduced to create lots of functions in which multiplier frames shape an essential structure, including digital signal processing (DSP) systems and analytical approaches. The benefit of floating point representation across a fixed point (and integer) view is that a wider range of values can be represented. Since floating point numbers are stored in sign-magnitude type, the multiplier also requires unwritten integer numbers and standardization. The multiplier with the algorithm Revised Booth and save adder is one way to speed up the multiplier. The algorithm of Revised Booth reduces the number of incomplete products to create and is regarded as the quickest algorithm of propagation.
Keywords: Radix4 Booth Multiplier, Booth Algorithm, Partial Products Generation, Signed-Unsigned Multiplication.
Scope of the Article: Production.