VLSI Implementation of DWT Using Systolic Array Architecture
M.Nireesh Kumar1, J.Hemanth2, K.Durga Prasad3

1Mr. M. Nireesh Kumar, M. Tech. Student, Department of ECE, JPNCE, Mahbubnagar (Telangana), India.
2Mr. J. Hemanth, Asst. Prof. Department of ECE, Vemu IT, Chittoor (Andhra Pradesh), India.
3Mr. K. Durga Prasad, Assoc Prof Department of ECE, JPNCE, Mahbubnagar (Telangana), India.

Manuscript received on 18 October 2012 | Revised Manuscript received on 25 October 2012 | Manuscript published on 30 October 2012 | PP: 67-73 | Volume-1 Issue-4, October 2012 | Retrieval Number: D0332091412/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: This work presents an implementation of Discrete Wavelet Transform (DWT)using Systolic architecture in VLSI .This architecture consist of Input delay unit, filter, register bank and control unit. This performs the calculation of high pass and low pass coefficients by using only one multiplier. This architecture has been simulated and implemented in VLSI. The hardware utilization efficiency is more compared to the referred due to FBRA Scheme. The systolic nature of this architecture corresponding to a clock speed of 115.9 MHz has its advantage in Optimizing area, time and power. The architecture is simple, modular, and cancelable for computation of one, or multi-dimensional DWT.
Keywords: DWT, Six Tap FIR Filter, Systolic Array Architecture, Decomposition, FBRA.
Scope of the Article: Computer Architecture and VLSI