Double Precision Floating Point Fft Processor using Vedic Mathematics
Anitha R
Anitha R, Professor School of Electronics Engineering, VIT University, Vellore-632014, Tamil Nadu, India.

Manuscript received on November 12, 2019. | Revised Manuscript received on November 23, 2019. | Manuscript published on 30 November, 2019. | PP: 8533-8538 | Volume-8 Issue-4, November 2019. | Retrieval Number: C6590098319/2019©BEIESP | DOI: 10.35940/ijrte.C6590.118419

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Abstract: There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.
Keywords: DPFP, FFT, Vedic Mathematics, FPA, RCA, MSB, IEEE-754..
Scope of the Article: Cryptography and Applied Mathematics.