A Novel Architecture for Low Power Adiabatic Cipher
Samik Samanta1, Rajat Mahapatra2, Ashis Kumar Mal3
1Samik Samanta, ECE Department, Neotia Institute of Technology, Management &Science, India.
2Rajat Mahapatra, ECE Department, National Institute of Technology, Durgapur, India.
3Ashis Kumar Mal, ECE Department, National Institute of Technology, Durgapur, India.

Manuscript received on November 12, 2019. | Revised Manuscript received on November 25, 2019. | Manuscript published on 30 November, 2019. | PP: 5619-5623 | Volume-8 Issue-4, November 2019. | Retrieval Number: C6462098319/2019©BEIESP | DOI: 10.35940/ijrte.C6462.118419

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: AES stands for Advanced Encryption Standard. It is widely used in today’s various security applications. S-box method is the most common and important in today’s data security and embedded applications.. This S-box consumes a considerable percentage of power of the whole system. S-box is very prone to differential power attacks(DPA). DPA is the most threatening types of attacks in cryptographic systems. In this paper, we have implemented one positive polarity Reed Muller type S-box is implemented using adiabatic logic. Efficient charge recovery logic(ECRL)is used here. FinFET based ECRL is used to implement the S-box has been observed and calculated .The performance of ECRL based S-box is compared with conventional CMOS based S-box. The statistical parameters for DPA cipher design are also analyzed.
Keywords: Adiabatic, Finfet, CCS, SCRL, Power Clock..
Scope of the Article: Network Architectures.