A Varying Processor Cache Sets Architecture
S Subha

S Subha, Department of IT, School of Information Technology and Engineering, Vellore Institute of Technology, Velloe, T.Nadu, India.
Manuscript received on 02 August 2019. | Revised Manuscript received on 06 August 2019. | Manuscript published on 30 September 2019. | PP: 6141-6145 | Volume-8 Issue-3 September 2019 | Retrieval Number: C5679098319/2019©BEIESP | DOI: 10.35940/ijrte.C5679.098319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Any processor cache has three parameters capacity, line size and associativity. Usually all three are fixed at design time. Algorithms to have variable cache sets are proposed in literature. This paper proposes a method to have variable cache sets logically. The cache comes with fixed sets. The cache is visualized to have logically any number of sets greater than or equal to one. An algorithm for line placement/replacement is proposed in this paper for this model. The proposed model is simulated with SPEC2K benchmarks using Simplescalar Toolkit for two level inclusive set associative cache system. A power saving of 8.4% for L1 cache size 512×4, 17.58% for 1024×4 and 31.3% for 2048×4 is observed compared with traditional set associative cache of same size. A power saving of 7.53% compared with model proposed in literature for L1 size 512×4, 7.64% for 1024×4 and 7.645% for 2048×4 is observed. The L2 cache size is fixed at 2048×8. The average memory access time (AMAT) is found to degrade compared with conventional set associative cache by 19.63% for L1 size of 512×4, 24.68% for 1024×4 and 2048×4. (Abstract)
Keywords: Average Memory Access Time, Power, Set Associative Cache, Variable Processor Cache Sets

Scope of the Article:
Predictive Analysis