Analytical Modeling Of Adiabatic Logic With The Effects And Analysis Of Performance Parameter Variations
Samik Samanta1, Rajat Mahapatra2, Ashis Kumar Mal3

1Samik Samanta, department Management and Science Neotia Institute of Technology,Kolkata. India.
2Rajat Mahapatra, Professor in ECE department of National Institute of Technology, Durgapur west Bengal. India.
3Ashis Kumar , Professor in ECE department of National Institute of Technology, Durgapur. west Bengal. India.

Manuscript received on 01 August 2019. | Revised Manuscript received on 06 August 2019. | Manuscript published on 30 September 2019. | PP: 3910-3914 | Volume-8 Issue-3 September 2019 | Retrieval Number: C5122098319/2019©BEIESP | DOI: 10.35940/ijrte.C5122.098319
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Abstract: Adiabatic or energy recovery circuits are based on recycling the energy stored in nodal capacitances. For a given amount of energy stored in nodal capacitance, the energy drawn from the source depends on the rate of drawing the charge from the source. Power drawn from the source will be lower if the rate of charging is lower. The efficiency of charging of adiabatic circuits depends on how slowly the capacitance is being charged. We have presented one analytical model of adiabatic logic circuit and find out the expressions for power dissipations in charging and discharging phases. From the expression conclusions on design parameters are made. We have also examined the power dissipation of the adiabatic circuits with the variation of some device parameters like width of the transistors, load capacitance, power clock frequency and input data frequency.
Keywords: Adiabatic, CMOS, PMOS, NMOS, Charge, Power Clock

Scope of the Article:
Measurement & Performance Analysis