Design and Implementation of Radix-2 Modified Booth’s Encoder using FPGA and ASIC Methodology
Vasudeva G, Department of ECE, Don Bosco Institute of Technology, Bangalore-74 (Karnataka), India.
Manuscript received on 23 July 2015 | Revised Manuscript received on 30 July 2015 | Manuscript published on 30 July 2015 | PP: 43-47 | Volume-4 Issue-3, July 2015 | Retrieval Number: C1459074315©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents the design and implementation of signed-unsigned Modified Booth Encoding (SUMBE) multiplier. The present Modified Booth Encoding (MBE) multiplier and the Baugh-Wooley multiplier perform multiplication operation on signed numbers only. Therefore, this paper presents the design and implementation of SUMBE multiplier. The modified Booth Encoder circuit generates half the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the SUMBE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. The proposed radix-2 modified Booth algorithm MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC.The Simulation results are obtained from MODELSIM and Physical design is done from encounter tool from cadence also area, power and timing reports are obtained from RTL Compiler from cadence.
Keywords: CLA, CSA, SUMBE, Booth Encoder
Scope of the Article: Low-power design