Coherent Circuits for Parallel Bit-Reversal
S. Aruna Mastani1, G. Deepa2
1G. Deepa, M.Tech, VLSI System Design, Jawaharlal Nehru Technological University, Anantapuramu (AP), India.
2Dr. S. Aruna Mastani, Department of ECE, Jawaharlal Nehru Technological University, Anantapuramu (AP), India.
Manuscript received on 13 June 2022 | Revised Manuscript received on 17 June 2022 | Manuscript Accepted on 15 July 2022 | Manuscript published on 30 July 2022 | PP: 69-72 | Volume-11 Issue-2, July 2022 | Retrieval Number: 100.1/ijrte.B71040711222 | DOI: 10.35940/ijrte.B7104.0711222
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The Fast Fourier Transform is incomplete without bit-reversal. Novel parallel circuits for calculating bit reversal on data which is coming parallel are presented in this paper. The circuits are simplest, consisting of memories and multiplexers, and have the benefit of requiring the fewest multiplexers of all architectures for parallel bit reversal thus far, and tiny overall memory.
Keywords: Bit reversal, Fast Fourier Transform, pipeline architectures.
Scope of the Article: Computer Architecture and VLSI