FPGA Implementation of Memory Bists using Single Interface
P. Ramakrishna1, T. Vamshika2, M. Swathi3

1P. Ramakrishna, Associate professor, Department of Electronics and Communication Engineering, Anurag University, Hyderabad, India.
2T. Vamshika, P.G. Scholar, Department of Electronics and Communication Engineering, Anurag University, Hyderabad, India.
3M. Swathi, Assistant professor, Department of Electronics and Communication Engineering, Vignana Bharathi Institute of Technology, Hyderabad, India. 

Manuscript received on August 01, 2020. | Revised Manuscript received on August 05, 2020. | Manuscript published on September 30, 2020. | PP: 55-58 | Volume-9 Issue-3, September 2020. | Retrieval Number: 100.1/ijrte.B3975079220 | DOI: 10.35940/ijrte.B3975.099320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The development of IC integration technologies leads to an extensive use of memories and buffers in different memory intensive applications. Therefore, probability of occurrence of fault in every single read and writes operation is increased in Memory BIST (MBIST). There were many testing approaches that were developed for efficient testing and diagnosis of fault. However, all algorithms are not strengthened enough to detect all possible faults that may be present due to fabrication errors or environmental disturbance. Keeping this in mind and taking the possibility of development of efficient algorithm a hybrid memory testing algorithm is presented. To overcome those drawbacks, pipelining based MBIST designed to detect the all the types of memory faults by utilizing March-C testing algorithm. By introducing the Pipelining approach, majorly path delays are reducing. The proposed architecture designed and verified using Xilinx ISE environment under various testing methods with respect to the different category of memories. The simulation and synthesis results shows that the proposed method shows the enhanced performance with the hardware resource utilization and delay consumption compared to the conventional approaches.