Simplified on-The-Fly IAG QPP Interleaver for Turbo Channel Coding Scheme
E. Sujatha1, C. Subhas2, M. N. Giri Prasad3
1E. Sujatha, Dept. of ECE, Sree Vidyanikethan Engineering College, Tirupati, JNTUA, Anantapuramu, India.
2Dr. C. Subhas, Dept. of ECE, JNTUA College of Engineering, Kalikiri, India.
3 Dr. M. N. Giri Prasad, Dept. of ECE, JNTUA College of Engineering, Anantapuramu, India.
Manuscript received on 5 August 2019. | Revised Manuscript received on 11 August 2019. | Manuscript published on 30 September 2019. | PP: 1443-1448 | Volume-8 Issue-3 September 2019 | Retrieval Number: B3721078219/19©BEIESP| DOI: 10.35940/ijrte.B3721.098319
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Abstract: Interleaver is an indispensable component in the design of Turbo encoder and Turbo Decoder. QPP interleaver is a 3GPP specified conflict free interleaver for turbo channel coding scheme for all code block sizes of 40 to 6144. Thus the efficient design of a conflict free reconfigurable QPP interleaver for turbo encoder and turbo decoder is a pre-eminent task in turbo channel coding scheme. In this article, Design of a simplified reconfigurable (40 to 6144 block sizes) Recursive QPP interleaver for computation of address locations to minimize the computational complexity and to avoid storage of interleaver tables has been presented. The proposed interleaver will be further integrated in the design and implementation of high throughput parallel turbo decoder. The proposed design is synthesized and implemented using 28nm CMOS technology Zynq Zed FPGA and achieved low processing timing constraints, utilization and power constraints compared with other conventional designs.
Keywords: Interleaver, Memory contention, Turbo codes, QPP.
Scope of the Article: Network Coding