Pair Wise Swapping Based Hypergraph Parti-tioning Algorithms for VLSI Design
Er Mitali Sinha, Department of Computer Science & Engineering, Parala Maharaja Engineering College Affiliated to Biju Patnaik Uni-Versity of Technology, Berhampur, Odisha, India
Manuscript received on 16 March 2019 | Revised Manuscript received on 22 March 2019 | Manuscript published on 30 July 2019 | PP: 5589-5593 | Volume-8 Issue-2, July 2019 | Retrieval Number: B3612078219/19©BEIESP | DOI: 10.35940/ijrte.B3621.078219
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A VLSI integrated circuit is the most signifi-cant part of electronic systems such as personal computer or workstation, digital camera, cell phone or a portable computing device, and automobile. So development within the field of electronic space depends on the design planning of VLSI integrated circuit. Circuit partitioning is most important step in VLSI physical design process. Many heuristic partitioning algorithms are proposed for this problem. The first heuristic algorithm for hypergraph partitioning in the domain of VLSI is FM algorithm. In this paper, I have proposed three varia-tions of FM algorithm by utilizing pair insightful swapping strat-egies. I have played out a relative investigation of FM and my proposed algorithms utilizing two datasets for example ISPD98 and ISPD99. Test results demonstrate that my proposed calcula-tions outflank the FM algorithm.
Index terms: Block, Graph, Hypergraph, Netcut, Netlist, VLSI.
Scope of the Article: Algorithm Engineering