RHBD Charge Pump PLL based 2.4 GHz Frequency Synthesizer
Varsha Prasad1, S Sandya2
1Varsha Prasad, Department of Educational Credential Evaluators, Nitte Meenakshi Institute of Technology, Bangalore, India.
2Dr S Sandya, Department of Educational Credential Evaluators, Nitte Meenakshi Institute of Technology, Bangalore, India.
Manuscript received on 11 March 2019 | Revised Manuscript received on 16 March 2019 | Manuscript published on 30 July 2019 | PP: 3984-3995 | Volume-8 Issue-2, July 2019 | Retrieval Number: B3017078219/19©BEIESP | DOI: 10.35940/ijrte.B3017.078219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Frequency Synthesizer forms the heart of electronic communication system. Phase Locked Loop (PLL) based Frequency Synthesizers over the years has become the ubiquitous solution for generation of stable clock source. But it is a challenging task to design and develop PLL to be used in radiation environment such as in satellites, space systems and military electronics. Since impact of radiation strike on PLL is said to introduce transient faults resulting in increased timing jitter, distortion in phase, and bit flips. One or more of the above said effects can initiate false triggering which may result in incorrect data to be latched, loss of synchronization in data processing and networking. This may lead to catastrophic effect. Hence, as the stability of frequency synthesizer is of vital importance, there is a stressful need for design of radiation hard, fault tolerant frequency synthesizer. With this motivation, in this paper, a radiation hard CMOS Charge Pump PLL is designed to synthesize a 2.4GHz frequency source using 20MHz reference input frequency. The proposed radiation hard PLL design uses a hybrid Radiation Hardening By Design (RHBD) fault tolerant technique combined with redundancy, hence offering a twofold level of fortification from radiation spikes. Cadence tool was used for simulation. The PLL designed has exhibited satisfactory performance. The RHBD Charge Pump PLL in presence of radiation strike resulted in rms jitter of 128.9ps, phase noise of -94.03dbc/Hz and settling time of 159ns against the IEEE 802.11b/g standard requirement of 250ps jitter, -110dbc/Hz phase noise and 10us setting time.
Keywords: SET, Charge Pump PLL, Jitter, Phase Noise, Frequency Synthesis, SEE, TID Radiation Tolerant, RHBD, Ring VCO
Scope of the Article: Frequency Selective Surface