Design of High-Speed H.265 Sample Adaptive Offset Estimation for Ultra-Hd TV Encoding using Clock Synchronization Code
S. Shiyamala1, Reicelin Rani2
1Dr.S. Shiyamala, Department of Electronics and Communication Engineering, Vel Tech Rangarajan. Dr.Sagunthala R&D Institute of Science and Technology, Chennai, TN, India.
2Ms. Reicelin Rani, Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Chennai, TN, India.
Manuscript received on 08 March 2019 | Revised Manuscript received on 16 March 2019 | Manuscript published on 30 July 2019 | PP: 719-724 | Volume-8 Issue-2, July 2019 | Retrieval Number: B1728078219/19©BEIESP | DOI: 10.35940/ijrte.B1728.078219
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Sample adaptive offset (SAO) is a recently presented in-circle separating segment in H.265/High Efficiency Video Coding (HEVC). SAO adds to a striking coding effectiveness enhancement; the estimation of SAO parameters commands the multifaceted nature of in-circle sifting in HEVC encoding. Double clock engineering that procedures statistics collection (SC) and parameter decision (PD), the two principle useful squares of SAO estimation, at high-and low-speed timekeepers, separately. Such a technique decreases the general zone by 56% by tending to the heterogeneous information streams of SC and PD. This exploration work endeavors to ad lib the working clock speed by adjusting a double clock synchronizer VLSI structure of H.265 ultra HD encoder and control minimization. To additionally enhance the territory and power productivity, calculation engineering co-improvements are connected, including a coarse range selection (CRS) and an accumulator bit width reduction (ABR). They together may accomplish another 25% territory decrease. The proposed VLSI configuration is fit for handling 8k at 120-outlines/s encoding.
Index Terms: ADPLL, H.265, Power Dissipation, Unsynchronized Clock.
Scope of the Article: Adaptive Systems