Architectural Design of Effective Edge Preserving Median Filter with Error Correction System
Vanathi M1, A. Kaleel Rahuman2

1Vanathi M, PG Student, Department of VLSI System, PSNA College of Engineering, Dindigul (Tamil Nadu), India.
2Dr. A. Khaleel Rahuman, Associate Professor, Department of ECE, PSNA College of Engineering, Dindigul (Tamil Nadu), India.
Manuscript received on 21 October 2019 | Revised Manuscript received on 25 October 2019 | Manuscript Published on 02 November 2019 | PP: 4057-4067 | Volume-8 Issue-2S11 September 2019 | Retrieval Number: B15930982S1119/2019©BEIESP | DOI: 10.35940/ijrte.B1593.0982S1119
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Abstract: Designing of Median filter that can process 36 pixels at a time with edge preservation similar to a filter of size 9. Median sorting is done using Modified minimum exchange sorting method which attracts double the amount of inputs in order to reduce number of comparators used for median filtering. For the same reason i.e. double the amount of inputs switching loss is high in the circuit therefore data driven clock gating (DDCG) is applied for SRAM to form data driven FIFO. Considering space radiation that could excite memory state, Addition of DMR (Double Modular Redundancy) in FPIC would rectify the soft error that could possibly occur due to radiation in space. Therefore proposed method is capable of producing sharp image, controlling switching loss, minimizes area, and reduces soft errors.
Keywords: FIFO, Median Filter, DDCG, DMR.
Scope of the Article: Low-power design