FPGA Implementation of Optimized The 64-BIT RC5 & RC6 Cryptography Encryption Algorithm
Rubina Soni1, Sarabjit Singh2

1Student Rubina Soni, ECE, PTU/ Guru Gobind Singh College of Engg. &Technology Talwandi Sabo/Bathinda, (Punjab), India.
2Sarabjit Singh, ECE Guru Gobind Singh College of Engg. &Tech, Talwandi Sabo. /Bathinda, (Punjab), India.

Manuscript received on 23 May 2015 | Revised Manuscript received on 30 May 2015 | Manuscript published on 30 May 2015 | PP: 68-71 | Volume-4 Issue-2, May 2015 | Retrieval Number: B1430054215©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In today’s era there is a great demand for secure communications systems, which in turns demand for real-time implementation of cryptographic algorithms. In this paper we present a hardware implementation of the RC6 & RC5 algorithm using VHDL Hardware Description Language. We also explore the competence of RC6 & RC5 from the hardware implementation perspective with Field Programmable Gate Arrays (FPGAs) as the end technology. FPGAs are highly attractive options for hardware implementations of encryption algorithms as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. Our analysis and synthesis studies of the ciphers will suggest that RC5 & RC6 are fast block ciphers, developed by RSA Security, which exploits data rotation to achieve a high level of nonlinearity. 128 bit key and 12 rounds of operation in the design will provide great security to the user’s data. The optimization of area, timing and power is done during physical design process.
Keyword: Cryptographic Algorithms, RC5, RC6,

Scope of the Article: Cryptography and Applied Mathematics