Design and Implementation of Rearrangable Non-Blocking Switching Network in VLSI
B. Swapna Rani1, C. Chitra2

1B. Swapna Rani, Associate Professor, TKRCET, Medbowli, Saroor Nagar, Hyderabad (Telangana), India.
2Dr. C. Chitra, Professor, SSSUTMS, Sehore, Bhopal (M.P), India.
Manuscript received on 17 October 2019 | Revised Manuscript received on 25 October 2019 | Manuscript Published on 02 November 2019 | PP: 2858-2863 | Volume-8 Issue-2S11 September 2019 | Retrieval Number: B13560982S1119/2019©BEIESP | DOI: 10.35940/ijrte.B1356.0982S1119
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Abstract: The main goal of this article is to implement an effective Non-Blocking Benes switching Network. Benes Switching Network is designed with the uncomplicated switch modules & it’s have so many advantages, small latency, less traffic and it’s required number of switch modules. Clos and Benes networks are play a key role in the class of multistage interconnection network because of their extensibility and mortality. Benes network provides a low latency when compare with the other networks. 8×8 Benes non blocking switching network is designed and synthesized with the using of Xilinx tool 12.1.
Keywords: Benes Network, Non-Blocking Switching Network, Clos Network, Blocking Network, Cross Bar Switch.
Scope of the Article: VLSI Algorithms