FPGA Implementation of Fault Tolerant Full Adder Design for High Speed VLSI Architectures
Somashekhar1, Vikas Maheshwari2, R. P. Singh3

1Somashekhar, Research Scholar, Department of ECE, SSSUTMS, Sehore (M.P), India
2Dr. Vikas Maheshwari, Associate Professor, Department of ECE, Bharat Institute of Engineering and Technology, Hyderabad (Telangana), India.
3Dr. R. P. Singh, Vice-Chancelor & Professor, Department of ECE, SSSUTMS, Sehore (M.P), India.
Manuscript received on 24 July 2019 | Revised Manuscript received on 03 August 2019 | Manuscript Published on 10 August 2019 | PP: 1325-1329 | Volume-8 Issue-2S3 July 2019 | Retrieval Number: B12480782S319/2019©BEIESP | DOI: 10.35940/ijrte.B1248.0782S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The essential goal is to distinguish and diminish the deficiencies in full Adder configuration making use of Self checking and Self Repairing Adder Block. The tempo of chip disappointment is straightforwardly relative to chip thickness. A framework should be flaw tolerant to diminish the frustration rate. The nearness of different troubles can demolish the usefulness of complete snake. This paper displays a region proficient flaw tolerant complete snake shape that may repair issues without interfering with the everyday assignment of a framework. The combo and duplicate is finished through way of making use of Xilinx ISE 14.7 and actualized on FPGA Spartan three.
Keywords: VLSI, Fault Tolerance, Full Adder, Self-Checking, Self Repairing, FPGA Spartan 3, Verilog, Xilinx ISE 14.7.
Scope of the Article: FPGAs