Research on Net Weighting Schemes in Performance Driven Global Routing
Geetanjali Udgirkar1, G. Indumathi2
1Geetanjali Udgirkar, CMR Institute of Technology, Bangalore (Karnataka), India.
2G. Indumathi, Cambridge Institute of Technology, Bangalore (Karnataka), India.
Manuscript received on 23 July 2019 | Revised Manuscript received on 03 August 2019 | Manuscript Published on 10 August 2019 | PP: 1145-1150 | Volume-8 Issue-2S3 July 2019 | Retrieval Number: B12120782S319/2019©BEIESP | DOI: 10.35940/ijrte.B1212.0782S319
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In today’s VLSI technology nodes, interconnect delay plays an important part in deciding the performance of the chip designs. Various methods are introduced at the level of placement and routing to address this problem. To address this problem at the level of global routing, net weighting methods are being explored in the industry and academia. We investigate four methods for weighting the critical nets during performance driven global routing. This paper presents a comparative study conducted on the four methods for net weighting proposed by us in our previous works.
Keywords: FPGA Routing, Net Weighting Methods.
Scope of the Article: FPGAs