Design of High Speed 32-bit Floating Point Multiplier using Urdhva Triyagbhyam Sutra of Vedic Mathematics
Sai Venkatramana Prasada G S1, G Seshikala2, Niranjana S3

1Sai Venkatramana Prasada G S, Research Scholar, School of E&C, Srinivas University, Mangaluru, Reva University, Bengaluru (Karnataka), India.
2Dr. G Seshikala, School of E&C, Reva University, Bengaluru (Karnataka), India.
3Dr. Niranjana S, Manipal Institute of Technology, MAHE, Manipal (Karnataka), India.
Manuscript received on 22 July 2019 | Revised Manuscript received on 03 August 2019 | Manuscript Published on 10 August 2019 | PP: 1064-1067 | Volume-8 Issue-2S3 July 2019 | Retrieval Number: B11990782S319/2019©BEIESP | DOI: 10.35940/ijrte.B1199.0782S319
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Abstract: Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.
Keywords: Floating Point Numbers, IEEE 754, Urdhva Triyagbhyam Sutra, Vedic Mathematics.
Scope of the Article: High Speed Networks