Estimation of Failure State of Buck Voltage Regulator
Gadila Prashanth Reddy1, Rangaiah L2, Justin Khoo3, Rishab Mukherjee4, Srinivasan5, Srikanth Kaniyanoor6

1Gadila Prashanth, Reddy, Research Scholar, Raja Rajeshwari College of Engineering College, Bengaluru (Karnataka), India.
2Rangaiah L, Raja Rajeswari College of Engineering College, Bengaluru (Karnataka), India.
3Justin Khoo, Intel Corporation Penang.
4Rishab Mukherjee, Bengal Institue of Technology, Hadia (West Bengal), India.
5Srinivasan, Intel Technology Pvt Ltd.
6Srikanth Kaniyanoor, Intel Technology Pvt Ltd.
Manuscript received on 25 August 2019 | Revised Manuscript received on 11 September 2019 | Manuscript Published on 17 September 2019 | PP: 1858-1862 | Volume-8 Issue-2S8 August 2019 | Retrieval Number: B11690882S819/2019©BEIESP | DOI: 10.35940/ijrte.B1169.0882S819
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Abstract: Failure Mode Effect and Diagnostic Analysis is typical way to define Failure in time for a given design by performing fault analysis on each element of the design. However it may not always accurately determine the erroneous state for a self-correcting designs. An example of self-correcting designs is a buck voltage regulator in which output and required voltage are continuously compared to achieve desired output voltage. This paper assess the true failure state of a buck regulator by performing FMEDA in detail and with reasonable failure probability on each element a MARKOV state model is applied to estimate true failure state of buck VR.
Keywords: FMEDA, MARKOV Model, Buck VR.
Scope of the Article: Probabilistic Models and Methods