Design of a High Speed and Area Efficient Novel Adder for AES Applications
A. Radha1, K.S.N. Murthy2
1A. Radha, Research Scholar, Department of Engineering and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur (DT), Andhra Pradesh, India.
2K.S.N. Murthy, Professor, Department of Engineering and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur (DT), Andhra Pradesh, India.
Manuscript received on 01 March 2019 | Revised Manuscript received on 07 March 2019 | Manuscript published on 30 July 2019 | PP: 5261-5265 | Volume-8 Issue-2, July 2019 | Retrieval Number: B1057078219/19©BEIESP | DOI: 10.35940/ijrte.B1057.078219
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In the design of VLSI circuits, there is huge power consumption because of circuit complexity. It is known that the demand for portable equipment is rapidly increasing now a days. Recently power efficient circuit designs have been concentrated. In complex arithmetic circuits adder is the most important building block. These are widely used in some other applications also like Central Processing Units, Arithmetic Logic Units and floating-point units. In case of cache memory access and in digital signal processing, these are used for address generation. Adders are most significant in control systems also. The speed of a processor and system accuracy is based on the performance of this adder. Regularly, Ripple Carry Adder is elected for two N-bit numbers adder due to fast design time of these RCAs among various other types of adders. Even though if RCA has fast design time, but it is limited in time because of that each full adder must wait for the carry bits of previous full adder blocks. A carry tree adder is proposed in this paper which is efficiently implemented technique at gate level for decreasing the delay and decreasing the memory usage.
Key Terms: Carry Tree Adder, CLA, RCA, Black Cell, Gray Cell.
Scope of the Article: High Speed Networks