A Low-Cost Complexity Intra Prediction Hardware Architecture for HEVC Decoder
Hongkyun Jung1, Kwangki Ryoo2

1Hongkyun Jung, Large Touch Team, Silicon Works, Seoul, South Korea.
2Kwangki Ryoo, Department of Information and Communication Engineering, Hanbat National University, Daejeon, South Korea.
Manuscript received on 17 August 2019 | Revised Manuscript received on 27 August 2019 | Manuscript Published on 16 September 2019 | PP: 95-100 | Volume-8 Issue-2S6 July 2019 | Retrieval Number: B10180782S619/2019©BEIESP | DOI: 10.35940/ijrte.B1018.0782S619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: High Efficiency Video Coding (HEVC) adopts new techniques to reduce bit-rate by 50% over a previous video compression standard. The number of intra prediction modes in HEVC is 35 modes and increased compared with the compression. Therefore, hardware architecture with common equation and a fast filter coefficient generation algorithm is proposed for low complexity intra prediction hardware. The proposed architecture performs a smoothing filter, interpolation filter, generation of predicted pixels with only Common Operation Unit (COU). Various equations in intra prediction for smoothing filter of reference samples, calculating the average of the reference samples, generating predicted pixels and filtering predicted pixels is modified to one common equation. The common operation unit using a common equation in intra prediction hardware architecture reduces hardware area and the number of computational operators to perform various equations. COU uses 2 multipliers, 9 adders, 3 shifters and generates 1 predicted sample in planar mode and 2 predicted samples in the other mode. Also, COU generates 2 filtered reference samples in filtering operation of reference samples and the average of 4×4 PU in DC mode. The fast filter coefficient generation algorithm reduces processing time by using only Look-Up Table (LUT) and adders, instead of multiplying operation and the number of computational operators. The number of gates of the architecture is 45.6k. The number of gates in the proposed intra prediction hardware is 36.7% less than previous architecture.
Keywords: HEVC, Intra Prediction, Common Operation Unit, Fast Filter Coefficient Generation, Hardware Architecture.
Scope of the Article: Regression and Prediction