Implementation of RNG in FPGA using Efficient Resource Utilization
D. S. Monisha1, R. Shantha Selva Kumari2
1Ms. D. S. Monisha, M.E. Student, Mepco Schlenk Engineering College, Sivakasi (Tamil Nadu), India.
2Dr. R. Shantha Selva Kumari, Department of ECE., Mepco Schlenk Engineering College, Sivakasi (Tamil Nadu), India.
Manuscript received on 21 May 2013 | Revised Manuscript received on 28 May 2013 | Manuscript published on 30 May 2013 | PP: 90-95 | Volume-2 Issue-2, May 2013 | Retrieval Number: B0606052213/2013©BEIESP
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Computers’ required random numbers initially, for simulations and numerical computations like Monte Carlo calculations. Random number generators offer an important contribution to many communication systems for security. They are critical components in computational science. However the tradeoff between quality and computational performance is an issue for many numerical simulations. FPGA optimized RNGs are efficient in terms of resources than other types of softwarebased RNGs which means that they can take advantage of bitwise operations and FPGA based specific features. One of the types of FPGA based RNG called a LUT-SR RNG is illustrated using an algorithm. Shift registers are used to improve mixing rate between numbers. Results will be misleading when correlations exist between the random numbers and hence permutations are used. The LUTs are configured into shift registers. The algorithm is simplified based on the architecture such that it ensures longer periods. A generator with a period of can be implemented and provides r random output bits. This provides a good quality balance compared to previous generators. The critical path between all registers is a single LUT. The program is run in ModelSim 6.4a and implementation is done using Xilinx PlanAhead Virtex5 kit.
Keywords: Random Number Generator (RNG), Field Programmable Gate Arrays (FPGA), SIMD, Look up Table, Shift Register(LUT SR).
Scope of the Article: QOS And Resource Management