Performance of Mixed-MWCNT Structures as VLSI Interconnect for Nanometer Technology Nodes
Padeep Kumar Jindal1, K.S. Sandha2
1Pardeep Kumar Jindal, ECED, Thapar Institute of Engineering & Technology, Patiala, India,
2K.S. Sandha, ECED, Thapar Institute of Engineering & Technology, Patiala, India.

Manuscript received on 01 April 2019 | Revised Manuscript received on 07 May 2019 | Manuscript published on 30 May 2019 | PP: 2708-2713 | Volume-8 Issue-1, May 2019 | Retrieval Number: A1328058119/19©BEIESP
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Abstract: In this paper, performance of Mixed-MWCNTB (MMB) as global level interconnect length at nano-meter technology nodes has been studied. An equivalent single conductor (ESC) model for MMB structure as interconnect has been proposed. The parasitic of MMB structure as interconnect are calculated for variable length at different technology nodes. These parasitic are used to evaluate the performance of MMB and Copper as interconnect. The performance in terms of delay and power delay product (PDP) is evaluated using simulation Tanner tool. The analysis has been done for global interconnect length 400 to 2000μm at technology nodes as 32, 22 and 16nm. Further, similar analysis is carried out for copper as interconnect and the obtained results have been compared with proposed MMB as VLSI interconnect. The result reveals that MMB offers less resistance as compared to copper interconnect. The comparative analysis shows that the delay and PDP which is lower than copper for variable global interconnect length at all three technology nodes considered in this work. As a result, the MMB structure can be recommended as substitute for conventional copper as future VLSI interconnect material for high performance IC design at nanometer technology nodes.
Index Terms: Delay, Interconnects, Power, Technology Nodes

Scope of the Article: Performance Evaluation of Networks