Validation of Hybrid Network-on-Chip Architecture for Optimized Performance using BookSim Simulator
Talla Vamshi1, T. Satya Savithri2

1Talla Vamshi*, Department of ECE, Talla Padmavathi College of Engineering, Warangal, India.
2Dr. T. Satya Savithri, Department of ECE, Jawaharlal Nehru Technological University, Hyderabad, India.
Manuscript received on March 12, 2020. | Revised Manuscript received on March 25, 2020. | Manuscript published on March 30, 2020. | PP: 3393-3397 | Volume-8 Issue-6, March 2020. | Retrieval Number: F8858038620/2020©BEIESP | DOI: 10.35940/ijrte.F8858.038620

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Abstract: Various complex integrated circuits suffer from the issues like poor connectivity, higher energy consumption and design productivity. One of the best solutions could be Network-on-Chip architecture which could solve the above issues. The Network-on-Chip architecture should be modelled and simulated well to evaluate the performance and analyse the cost. This paper presents a method to validate the proposed Network-on-Chip architecture with direct sequence spread spectrum using BookSim simulator. This simulation aims at validating the network parameters like packet latency and network latency. The detailed architectural parameters are compared and presented in this paper.
Keywords: Central Key Scheduler, Network-on-Chip, Processing Element, Ring Key Scheduler, System-on-Chip.
Scope of the Article: Open Models and Architectures.