An Area Efficient Wallace Tree Multiplier using Modified Full Adder
Abdul Bari M.1, Baskaran M.2, Siva Nandini B.3
1Abdul Bari M., Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, Tamil Nadu, India.
2Baskaran M., Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, Tamil Nadu, India.
3Siva Nandini B., Assistant Professor, Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, Tamil Nadu, India.
Manuscript received on March 12, 2020. | Revised Manuscript received on March 25, 2020. | Manuscript published on March 30, 2020. | PP: 3383-3386 | Volume-8 Issue-6, March 2020. | Retrieval Number: F8814038620/2020©BEIESP | DOI: 10.35940/ijrte.F8814.038620
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Multipliers play a significant task in digital signal processing applications and application-specific integrated circuits. Wallace tree multipliers provide a high-speed multiplication process with an area-efficient strategy. It is realized in hardware using full adders and half adders. The optimization of adders can further improve the performance of multipliers. Wallace tree multiplier with modified full adder using NAND gate is proposed to achieve reduced silicon area, high speed and low power consumption. The conventional full adder implemented by XOR, AND, OR gates is replaced by the modified full adder realized using NAND gate. The proposed Wallace tree multiplier includes 544 transistors, while the conventional Wallace tree multiplier has 584 transistors for 4-bit multiplication.
Keywords: Wallace Tree Multiplier, Application – Specific Integrated Circuits, Area-Efficient Strategy, Transistors.
Scope of the Article: Innovative Mobile Applications.