Design of Static CMOS 16 Bit High Speeds and Low Power Consumption Hybrid Adder Circuit using Brent Kung Adder
M. Ramana Reddy

M.Ramana reddy*, Dept of ECE, CBIT (A), Osmania University Hyderabad, INDIA City, Country.

Manuscript received on February 12, 2020. | Revised Manuscript received on February 21, 2020. | Manuscript published on March 30, 2020. | PP: 300-310 | Volume-8 Issue-6, March 2020. | Retrieval Number: E6559018520/2020©BEIESP | DOI: 10.35940/ijrte.E6559.038620
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Abstract: This paper presents a static sixteen Bit CMOS Brent kung adder shape was designed, which famous a higher pace and decrease strength intake in comparison with those of the ripple deliver adders. The pace enhancement changed into done through modifying the shape through thru adding a Brent Kung adder, complete adders the usage of (28 transistor, Boolean exact judgment) that is masses speeder whilst in comparison to ripple supply adder and These pace adders will bring about growth in DSP processors. The time delays and power consumptions are lots much less with unique adders with the aid of implementation of 180nm Cadence device.
Keywords: Brent Kung adder, full adders, CADENCE, Time delay, Power Consumptions.
Scope of the Article: Waveform optimization for wireless power transfer.