Minimum Power Consumption High Efficiency Bypassing-Based 2D Multiplier Design using 65nm CMOS Technology
K. Paramasivam1, Suresh Kumar N2
1K. Paramasivam, Department of Electrical and Electronics Engineering, Kumaraguru College of Technology, Coimbatore (Tamil Nadu), India.
2Suresh Kumar N, Department of Electronics and Communication Engineering, MAM School of Engineering, (Tamil Nadu), India.
Manuscript received on 11 December 2018 | Revised Manuscript received on 22 December 2018 | Manuscript Published on 09 January 2019 | PP: 119-123 | Volume-7 Issue-4S November 2018 | Retrieval Number: E1883017519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Presently, in VLSI design, Power management has turn out to be a major issue. In this research, a Minimum Power Consumption Bypassing-Based 2D Multiplier Design using 65nm CMOS Technology was presented. When matched up with digital row bypassing based multiplier design, digital column bypassing based multiplier design and digital low power two-dimension bypassing based multiplier design, the experimentation outcomes shown our presented Multiplier Design decreases 31.2% of the power dissipation for 4*4 Multiplier.
Keywords: Low Power, Multiplier, CMOS, Bypassing.
Scope of the Article: Low-power design